1. Field of the Invention
The present invention generally relates to instruction control units provided in the central processing units of computers, and particularly relates to an instruction control system that suppresses or nullifies erroneous instruction fetch requests and operand requests at the time of failure of branch prediction until it becomes possible to issue another instruction fetch request to the memory in an instruction control device of an out-of-order type having a branch prediction function.
2. Description of the Related Art
Control methods for controlling instruction control units (instruction units) provided in the central processing units of computers include an in-order method and an out-of-order control method. In the in-order control method, instructions are executed in the order in which they are stored in memory.
In the out-of-order control method, on the other hand, a plurality of instructions following a given instruction are successively thrown into the execution pipeline for execution of these instructions without waiting for the completion of the execution of the given instruction. Namely, instructions are executed while changing the order in which the instructions are executed in the execution pipeline by a plurality of computing units. In the end, the execution of the instructions as a whole finishes in an in-order state. That is, the entry of instructions into the execution pipeline and the completion of the instructions coming out of the execution pipeline are performed in the given order while the instructions are actually executed out of turn inside the execution pipeline.
Even in the out-of-order control method, the results of execution of a preceding instruction may affect the execution of the following instructions. In such a case, the following instructions cannot be executed until the execution of the preceding instruction comes to end. That is, a wait for the completion of the preceding instruction continues as long as it is necessary.
This is frequently observed with respect to the execution of branch instructions as in the case in which the preceding instruction noted above is a branch instruction. Branch instructions include a conditional branch instruction and an unconditional branch instruction. Among the branch instructions, the conditional branch instruction, in particular, is not determinative as to whether branching takes place or not until branch conditions are fixed upon the completion of those instructions which are being executed prior to the branch instruction and which affect the branch conditions.
Since the sequence of instructions following this conditional branch instruction cannot be determined, following instructions cannot be thrown into the execution pipeline, which thus results in the suspension of processing. As a result, the performance of the system drops.
Such drop in the performance equally occurs in instruction control units employing other control methods, and is a common issue in the field of instruction control units. In order to solve this issue of a performance drop caused by branch instructions, a prediction mechanism for predicting the execution of a branch instruction is typically provided in the instruction control unit in an attempt to increase the execution speed of branch instructions.
In the out-of-order control method having the branch prediction mechanism, a plurality of branch instructions are thrown into the execution pipeline according to the results of branch prediction. The presence/absence of branching and the success/failure of branch prediction are determined successively for the branch instructions as branch conditions are successively determined for these branch instructions.
If a branch prediction by the branch prediction mechanism is correct, instructions following the predicted branch instruction thrown into the execution pipeline are correct. If the branch instruction is incorrect, however, the instructions following the predicted branch instruction are an erroneous instruction sequence, which needs to be erased from the execution pipeline. A correct instruction sequence then needs to be prepared for execution.
When a branch prediction fails, an instruction fetch is performed again. After it is found that a branch prediction by the branch prediction mechanism has failed, however, some time period may pass before an instruction fetch is performed again or before the erroneous instruction sequence is removed from the execution pipeline.
During such time period, instructions that are not to be executed are in existence in the execution pipeline. From these instructions that are not to be executed, operand requests may be issued. The same applies in the case of instruction fetches. That is, unnecessary requests are issued with respect to an instruction sequence that is not to be used. When unnecessary operand requests or instruction fetch requests are issued, needless replacement takes place in the cache memory, or instruction control resources such as computing units are needlessly consumed. This results in a performance drop.
When a check as to the branching of a branch instruction is made to ascertain that the branch prediction has filed, there is a need to reissue an instruction fetch request to the instruction fetch control unit. In order to reissue an instruction fetch request, however, the branch condition and the address of the branch destination need to be fixed. Further, even if the branch conditions are fixed and it is known that the branch prediction has failed, an instruction fetch request cannot be reissued unless the address of the branch destination is determined. During this time period, unfortunately, the instruction fetch control unit keeps issuing needless instruction fetch requests.
As previously described, instructions thrown into the execution pipeline based on erroneous prediction need to be removed from the pipeline when the branch prediction fails. In order to do this, the branch instruction for which the branch prediction has filed must come to an end first. Since instructions are completed in the in-order sequence, however, the instructions thrown into the execution pipeline cannot be removed from the pipeline unless the instructions preceding the branch instruction all come to an end. If the completion of the branch instruction for which branch prediction has failed is delayed, the instructions erroneously thrown into the execution pipeline may cause needless operand requests to be issued.